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AT86RF231
9.3.3
Interrupt Handling
Access conflicts may occur when reading and writing data simultaneously at the two indepen-
dent ports of the Frame Buffer, TX/RX BBP and SPI. Both of these ports have their own address
counter that points to the Frame Buffer's current address.
Access violations occurs during concurrent Frame Buffer read or write accesses, when the SPI
port's address counter value becomes higher than or equal to that of TX/RX BBP port.
While receiving a frame, primarily the data needs to be stored in the Frame Buffer before read-
ing it. This can be ensured by accessing the Frame Buffer 32 μs after IRQ_2 (RX_START) at the
earliest. When reading the frame data continuously the SPI data rate shall be lower than 250
kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame
Buffer read access Frame Buffer Empty indication may be used, for details refer to Section 11.7
“Frame Buffer Empty Indicator” on page 152 .
While transmitting an access violation occurs during a Frame Buffer write access, when the SPI
port's address counter value becomes less than or equal to that of TX BBP port.
Both these access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR)
interrupt when using the Frame Buffer access mode. Access violations are not indicated when
using the SRAM access mode.
Notes
? Interrupt IRQ_6 (TRX_UR) is valid 64 μs after IRQ_2 (RX_START). The occurrence of the
interrupt can be disregarded when reading the first byte of the Frame Buffer between 32 μs
and 64 μs after the RX_START interrupt.
? If a Frame Buffer read access is not finished until a new frame is received, a TRX_UR
interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher
than the effective PHY data rate. A minimum SPI clock rate of 1 MHz is recommended in this
case. Finally, the microcontroller should check the integrity of the transferred frame data by
calculating the FCS.
? When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be
higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU
data must be available in the Frame Buffer before SFD transmission is complete, which takes
176 μs (16 μs PA ramp up + 160 μs SHR) from the rising edge of SLP_TR pin (see Figure 7-
2 on page 39 ).
109
8111C–MCU Wireless–09/09
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